This application is related to U.S. patent application Ser. No. 07/986,490 commonly assigned to the assignee of the present application.
1. Field of the Invention
The present invention relates to digital data detectors, and more particularly to a digital data detector for detecting a data detection clock signal and digital data from a received digital signal in a digital data transmission system.
2. Description of the Related Art
There are various methods of detecting digital data from a received digital signal. One example is disclosed in the digital data detection apparatus of the aforementioned U.S. patent application Ser. No. 07/986,490. This apparatus detects digital data from a received digital signal as set forth in the following. In the following description, a "zero crossing point" refers to the point where a received signal crosses the zero level, and a "current sampling point" refers to a sampling point where the current phase is to be calculated. The current sampling point is represented by R.sub.i+1, the sampling point which is located one point before the current sampling point is represented by R.sub.i (referred to as the preceding sampling point hereinafter), the sampling point which is located two points before the current sampling point is represented by R.sub.i-1 (referred to as the second preceding sampling point hereinafter), and so on. The phase of sampling point R.sub.i is P.sub.i, and the amplitude value of the sampled data is S.sub.i.
First, a digital received signal is sampled at a frequency of m times (m&gt;1) a channel bit rate. It is assumed that a digital received signal is sampled at a frequency of two times the channel bit rate in the present specification (i.e., m=2).
The phase interval P between the zero crossing point of a received signal and the current sampling point R.sub.i+1 is obtained by the following equation (1) according to sampling data S.sub.i+1 of the current sampling point R.sub.i+1 and sampling data S.sub.i of the preceding sampling point R.sub.i. The phase of each sampling point is represented by the values of 0-N-1 obtained by equally dividing the channel bit interval by N. Therefore, in equation (1), N represents the channel bit interval, and N/2 represents half the channel bit interval. EQU P=.vertline.S.sub.i+1 .vertline./(.vertline.S.sub.i+1 .vertline.+.vertline.S.sub.i .vertline.).times.(N/2) (1)
Since the phase of a sampling point returns to 0 at the head of each channel bit interval, the calculation of a phase is carried out in modulo N (mod N) hereinafter.
If the phase of the zero crossing point is selected as a reference, and if it is supposed to be zero, the phase interval P yielded by equation (1) represents the instantaneous phase of the current sampling point R.sub.i+1 (referred to as the current instantaneous phase hereinafter).
Then, determination is made whether there is a zero crossing point immediately before the preceding sampling point R.sub.i. More specifically, determination is made whether there is a zero crossing point between the preceding sampling point R.sub.i and the second preceding sampling point R.sub.i-1.
If a zero crossing point is present, a predicted value Pd.sub.i+1 of the phase interval between sampling points R.sub.i+1 and R.sub.i is obtained by the following equation (2) using a phase P.sub.i of a sampling point R.sub.i (referred to as the preceding phase hereinafter) and a phase P.sub.i-j (referred to as at least the second preceding phase hereinafter) of a sampling point R.sub.i-j (j.gtoreq.2) which is located at least two points before the current sampling point R.sub.i+1. EQU Pd.sub.i+1 ={(P.sub.i -P.sub.i-j -((N/2.times.j) mod N)).times.L+N/2}mod N (2)
where "mod" is a remainder operator. More specifically, the calculated result of "x mod y" is the remainder of x divided by y. L is a constant number where 0&lt;L&lt;1.
When there is no zero crossing point, the predicted value Pd.sub.i+1 of the phase interval between the current sampling point R.sub.i+1 and the preceding sampling point R.sub.i is made equal to a predicted value Pd.sub.i of the phase interval between the preceding sampling point R.sub.i and the second preceding sampling point R.sub.i-1 as shown in the following equation (3). EQU Pd.sub.i+1 =P.sub.i ( 3)
A predicted value P.sub.i+1 ' of the current phase is obtained by the following equation (4) using the predicted value Pd.sub.i+1 of the phase interval obtained from equation (2) or (3) and the preceding phase P.sub.i. EQU P.sub.i+1 '=(P.sub.i +Pd.sub.i+1) mod N (4)
When there is a zero crossing point immediately before preceding the current sampling point R.sub.i+1, i.e., when there is a zero crossing point between sampling points R.sub.i+1 and R.sub.i, the current phase P.sub.i+1 is obtained by the following equation (5) using the predicted value P.sub.i+1 ' of the current phase obtained by equation (4) and the aforementioned current instantaneous phase P. EQU P.sub.i+1 ={(P-P.sub.i+1 ').times.K+P.sub.i+1 '}mod N (5)
where K is a constant corresponding to a loop gain (0&lt;K&lt;1).
When a zero crossing point is not present immediately before preceding the current sampling point R.sub.i+1, the current phase is made equal to the predicted value P.sub.i+1 ' of the current phase, as shown in the following equation (6). EQU P.sub.i+1 =P.sub.i+1 ' (6)
A data detection clock signal and digital data are detected according to the current phase P.sub.i+1, the preceding phase P.sub.i, conditions of clock signal extraction and data determination, and the current instantaneous phase thus obtained, i.e. the phase interval P between the zero crossing point and the current sampling point R.sub.i+1. The clock signal extraction conditions are shown in equations (7)-(9). EQU P.sub.i &gt;P.sub.i+1 and P.sub.i .gtoreq.N/2 and P.sub.i+1 .gtoreq.N/2(7) EQU P.sub.i &gt;P.sub.i+1 and P.sub.i &lt;N/2 and P.sub.i+1 &lt;N/2 (8) EQU P.sub.i &lt;P.sub.i+1 and P.sub.i &lt;N/2 and P.sub.i+1 .gtoreq.N/2(9)
Determination is made that a clock signal is present when the phase interval P between the zero crossing point and the current sampling point R.sub.i+1, the current phase P.sub.i+1, and the preceding phase P.sub.i satisfy at least one of the clock signal extraction conditions of equations (7)-(9).
The data determination condition is shown in the following equation (10). EQU P&gt;P.sub.i+1 -N/2 (10)
If equation (10) is met, the value of the digital data is the opposite of the MSB of sampling data Si, otherwise the MSB of Si.
The reason why the instantaneous phase P fluctuates due to noise and a wow and flutter in a received digital signal will be described hereinafter.
Referring to FIG. 1, the error .epsilon. between a correct instantaneous phase Pt and an instantaneous phase P calculated according to equation (1) is small when there is no noise and wow/flutter in a received digital signal. More specifically, the error .epsilon. is small between the phase interval between the point where the received digital signal crosses the reference level and the current sampling point R.sub.i+1, and the instantaneous phase P.
Referring to FIG. 2, the correct instantaneous phase Pt per se varies according to the fluctuation of a received digital signal itself when there is a wow and flutter in the received digital signal. Since instantaneous phase P calculated according to equation (1) follows this change, the error .epsilon. of the instantaneous phase P with respect to a correct instantaneous phase Pt is similarly small as in FIG. 1.
Referring to FIG. 3, instantaneous phase P fluctuates due to noise in a received digital signal although there is no fluctuation of the received digital signal per se. Therefore, the error .epsilon. between a correct instantaneous phase Pt and an instantaneous phase P calculated by equation (1) is large.
Mapping the fluctuation of an instantaneous phase P due to noise and wow/flutter into a frequency domain, fluctuation due to wow and flutter resides in a relatively low frequency range. In contrast, fluctuation due to noise is apt to increase as the frequency range becomes higher. It is desired that a digital data detector for detecting digital data from a received digital signal including noise and wow flutter obtains a clock signal that follows only the frequency band of fluctuation due to wow and flutter, and not the frequency band due to noise or the like.
The digital data detector disclosed in U.S. patent application Ser. No. 07/986,490 corresponds to a digital data reception signal with the above-described wow and flutter. However, there are still the following problems to be solved.
In recent years, there has been intensive efforts to reduce the size and cost of, for example, a magnetic tape recording/reproducing apparatus. In consequence, the signal to noise ratio (referred to as SNR hereinafter) of a received digital signal reproduced from a magnetic tape is degraded.
Reduction in SNR increases the possibility of an error in the detected digital data, resulting in decrease of the reliability of the system. This problem is encountered even in the digital data detector of the aforementioned U.S. patent application Ser. No. 07/986,490.